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D a t a s he e t , V e rs i o n 1 . 1, 28 S e p 2 0 0 5
F3
ICE3BS02L
Off-Line SMPS Current Mode Controller with integrated 500V Startup Cell and Latched off Mode
Power Management & Supply
Never
stop
thinking.
F3 latched off version Revision History: Previous Version: Page 2005-09-28 V1.0 Datasheet
Subjects (major changes since last revision)
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Edition 2005-09-28 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 Munchen
(c) Infineon Technologies AG 1999. All Rights Reserved.
Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
F3
ICE3BS02L
Off-Line SMPS Current Mode Controller with integrated 500V Startup Cell and Latched off Mode
Product Highlights
* Active Burst Mode to reach the lowest Standby Power Requirements < 100mW * Latched Off Mode and Auto Restart Mode to increase robustness and safety of the system * Adjustable Blanking Window for high load jumps to increase system reliability * PB-free Plating and RoHS compliant
test PG-DIP-8-6
Features
* * * * * * * * * * * * * * * * 500V Startup Cell switched off after Start Up Active Burst Mode for lowest Standby Power @ light load controlled by Feedback Signal Fast load jump response in Active Burst Mode 67kHz internally fixed switching frequency Latched Off Mode for Overtemperature Detection Latched Off Mode for Overvoltage Detection Latched Off Mode for Short Winding Detection Auto Restart Mode for Overload and Open Loop Auto Restart Mode for VCC Undervoltage Blanking Window for short duration high current User defined Soft Start Minimum of external components required Max Duty Cycle 72% Overall tolerance of Current Limiting < 5% Internal PWM Leading Edge Blanking Soft driving for low EMI
Description
The F3 Controller provides Active Burst Mode to reach the lowest Standby Power Requirements <100mW at no load. As the controller is always active during Active Burst Mode, there is an immediate response on load jumps without any black out in the SMPS. In Active Burst Mode the ripple of the output voltage can be reduced <1%. Furthermore, to increase the robustness and safety of the system, the device enters into Latched Off Mode in the cases of Overtemperature, Overvoltage or Short Winding. The Latched Off Mode can only be reset by disconnecting the main line. Auto Restart Mode is entered for cases like open loop or overload. By means of an internal precise peak current limitation, the dimension of the transformer and the secondary diode can be lowered which leads to more cost efficiency. An adjustable blanking window prevents the IC from entering Auto Restart Mode or Active Burst Mode unintentionally in case of high load jumps.
Typical Application
+
85 ... 270 VAC HV
C Bulk C VCC
Snubber
Converter DC Output
-
VCC
Startup Cell
PW M Controller Current Mode Precise Low Tolerance Peak Current Limitation
Gate CS R Sense
Power Management
Control Unit
Active Burst Mode Latched Off Mode Auto Restart Mode
FB SoftS C SoftS
GND
ICE3BS02L
F3 with Latch off Mode
Type ICE3BS02L
FOSC 67kHz
Package PG-DIP-8-6
Version 1.1
3
28 Sep 2005
F3 ICE3BS02L
Table of Contents 1 1.1 1.2 2 3 3.1 3.2 3.3 3.4 3.4.1 3.4.2 3.4.3 3.5 3.5.1 3.5.2 3.6 3.6.1 3.6.2 3.6.2.1 3.6.2.2 3.6.2.3 3.6.3 3.6.3.1 3.6.3.2 4 4.1 4.2 4.3 4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 4.3.6 5 Page
Pin Configuration and Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin Configuration with PG-DIP-8-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Representative Blockdiagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Startup Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 PWM Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 PWM-Latch FF1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Gate Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Current Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Leading Edge Blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Propagation Delay Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Adjustable Blanking Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Entering Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Working in Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Leaving Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Latched Off Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Auto Restart Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Supply Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PWM Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Driver Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 15 15 16 16 16 17 17 18 19
Outline Dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
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Pin Configuration and Functionality
1
1.1
Pin 1 2 3 4 5 6 7 8
Pin Configuration and Functionality
Pin Configuration with PG-DIP-8-6
1.2
Pin Functionality
Symbol SoftS FB CS HV HV Gate VCC GND
Function Soft-Start Feedback Current Sense High Voltage Input High Voltage Input Driver Stage Output Controller Supply Voltage Controller Ground
SoftS (Soft Start & Auto Restart Control) The SoftS pin combines the functions of Soft Start during Start Up and error detection for Auto Restart Mode. These functions are implemented and can be adjusted by means of an external capacitor at SoftS to ground. This capacitor also provides an adjustable blanking window for high load jumps, before the IC enters into Auto Restart Mode. FB (Feedback) The information about the regulation is provided by the FB Pin to the internal Protection Unit and to the internal PWMComparator to control the duty cycle. The FB-Signal controls in case of light load the Active Burst Mode of the controller. CS (Current Sense) The Current Sense pin senses the voltage developed on the series resistor inserted in the source of the external PowerMOS. If CS reaches the internal threshold of the Current Limit Comparator, the Driver output is immediately switched off. Furthermore the current information is provided for the PWM-Comparator to realize the Current Mode. Gate The Gate pin is the output of the internal driver stage connected to the Gate of an external PowerMOS. HV (High Voltage) The HV pin is connected to the rectified DC input voltage. It is the input for the integrated 500V Startup Cell. VCC (Power supply) The VCC pin is the positive supply of the IC. The operating range is between 8.5V and 21V. GND (Ground) The GND pin is the ground of the controller.
Package PG-DIP-8-6
SoftS
1
8
GND
FB
2
7
VCC
CS
3
6
Gate
HV
4
5
HV
Figure 1 Note:
Pin Configuration PG-DIP-8-6(top view) Pin 4 and 5 are shorted within the DIP 8 package.
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2
Figure 2
CBulk Snubber + Converter DC Output VOUT CVCC
Version 1.1
HV
Power Management Internal Bias Voltage Reference VCC 6.5V
85 ... 270 VAC
VCC Startup Cell GND
6.5V
RSoftS
3.25k
SoftS
Undervoltage Lockout
15V 0.72 8.5V
T2
T3 Power-Down Reset PWM Section Oscillator
Duty Cycle max
1V
Latched Off Mode Reset VVCC < 6V
Representative Blockdiagram
1 G3 Latched Off Mode Soft Start Soft-Start Comparator
Clock
T1
CSoftS
5k
VCC
4.4V Thermal Shutdown
Tj >140C
21V C7 & G7 Gate Driver & G9 1 G8 PWM Comparator C8 C11 & G5 Propagation-Delay Compensation
0.85V
C1
& G1 Spike Blanking 8.0us
S1
4.0V
C2
Representative Blockdiagram
6
Spike Blanking 190ns 1.66V Auto Restart Mode & G6 C10 x3.7 PWM OP C12 & G11 Current Mode & G10 Active Burst Mode 10k 1pF D1
1
FF1 S RQ
G2
Gate
5.4V
C3
6.5V
RFB
4.8V
C4
5k
C5
FB
1.32V
CS
RSense
10pF
4.0V
C6a
Vcsth Leading Edge Blanking 220ns 0.257V
Control Unit
3.4V
C6b
Current Limiting
Representative Blockdiagram
ICE3BS02L
F3 ICE3BS02L
28 Sep 2005
F3 ICE3BS02L
Functional Description
3
Functional Description
3.2
HV
Power Management
Startup Cell VCC
All values which are used in the functional description are typical values. For calculating the worst cases the min/max values which can be found in section 4 Electrical Characteristics have to be considered.
3.1
Introduction
Power Managem ent Internal Bias Latched Off Mode Reset VVCC < 6V Power-Down Reset Undervoltage Lockout 15V 8.5V
The F3 is the further development of the F2 to meet the requirements for the lowest Standby Power at minimum load and no load conditions. A new fully integrated Standby Power concept is implemented into the IC in order to keep the application design easy. Compared to F2 no further external parts are needed to achieve the lowest Standby Power. An intelligent Active Burst Mode is used for this Standby Mode. After entering this mode there is still a full control of the power conversion by the secondary side via the same optocoupler that is used for the normal PWM control. The response on load jumps is optimized. The voltage ripple on Vout is minimized. Vout is further on well controlled in this mode. The usually external connected RC-filter in the feedback line after the optocoupler is integrated in the IC to reduce the external part count. Furthermore a high voltage startup cell is integrated into the IC which is switched off once the Undervoltage Lockout onthreshold of 15V is exceeded. The external startup resistor is no longer necessary. Power losses are therefore reduced. This increases the efficiency under light load conditions drastically. The Soft-Start capacitor is also used for providing an adjustable blanking window for high load jumps. During this time window the overload detection is disabled. With this concept no further external components are necessary to adjust the blanking window. In order to increase the robustness and safety of the system, the IC provides 2 levels of protection modes: Latched Off Mode and Auto Restart Mode. The Latched Off Mode is only entered under dangerous conditions which can damage the SMPS if not switched off immediately. A restart of the system can only be done by disconnecting the AC line. The Auto Restart Mode reduces the average power conversion to a minimum under unsafe operating conditions. This is necessary for a prolonged fault condition which could otherwise lead to a destruction of the SMPS over time. Once the malfunction is removed, normal operation is automatically initiated after the next Start Up Phase. The internal precise peak current limitation reduces the costs for the transformer and the secondary diode. The influence of the change in the input voltage on the power limitation can be avoided together with the integrated Propagation Delay Compensation. Therefore the maximum power is nearly independent on the input voltage which is required for wide range SMPS. There is no need for an extra over-sizing of the SMPS, e.g. the transformer or PowerMOS.
Voltage Reference
6.5V
Auto Restart Mode
T1
Active Burst Mode
Latched Off Mode
SoftS
Figure 3 Power Management The Undervoltage Lockout monitors the external supply voltage VVCC. When the SMPS is plugged to the main line the internal Startup Cell is biased and starts to charge the external capacitor CVCC which is connected to the VCC pin. This VCC charge current which is provided by the Startup Cell from the HV pin is 1.05mA. When VVCC exceeds the onthreshold VCCon=15V the internal voltage reference and bias circuit are switched on. Then the Startup Cell is switched off by the Undervoltage Lockout and therefore no power losses present due to the connection of the Startup Cell to the bus voltage (HV). To avoid uncontrolled ringing at switch-on a hysteresis is implemented. The switch-off of the controller can only take place after Active Mode was entered and VVCC falls below 8.5V. The maximum current consumption before the controller is activated is about 160A. When VVCC falls below the off-threshold VCCoff=8.5V the internal reference is switched off and the Power Down reset let T1 discharging the soft-start capacitor CSoftS at pin SoftS.
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F3 ICE3BS02L
Functional Description
Thus it is ensured that at every startup cycle the voltage ramp at pin SoftS starts at zero. The internal Voltage Reference is switched off if Latched Off Mode or Auto Restart Mode is entered. The current consumption is then reduced to 300A. Once the malfunction condition is removed, this block will then turn back on. The recovery from Auto Restart Mode does not require disconnecting the SMPS from the AC line. In case Latched Off Mode is entered, VCC needs to be lowered below 6V to reset the Latched Off Mode. This is done usually by disconnecting the SMPS from the AC line. When Active Burst Mode is entered the internal Bias is switched off in order to reduce the current consumption below 1.05mA while keeping the Voltage Reference still active as this is necessary in this mode.
place between 1V and 4V. Above VSoftsS = 4V there is no longer duty cycle limitation DCmax which is controlled by comparator C7 since comparator C2 blocks the gate G7 (see Figure 4). This maximum charge current in the very first stage when VSoftS is below 1V, is limited to 1.32mA.
VSoftS
max. Startup Phase 5.4V 4V
3.3
Startup Phase
6.5V 3.25k
1V max. Soft Start Phase
DCmax
DC1
t
RSoftS
T2 T3 1V
DC2
SoftS
CSoftS Soft Start C7 Soft-Start Comparator & G7 C2 4V
t1
Figure 5
Gate Driver
t2 t
Startup Phase
0.85V x3.7 PWM OP CS
By means of this extra charge stage, there is no delay in the beginning of the Startup Phase when there is still no switching. Furthermore Soft Start is finished at 4V to have faster the maximum power capability. The duty cycles DC1 and DC2 are depending on the mains and the primary inductance of the transformer. The limitation of the primary current by DC2 is related to VSoftS = 4V. But DC1 is related to a maximum primary current which is limited by the internal Current Limiting with CS = 1V. Therefore the maximum Startup Phase is divided into a Soft Start Phase until t1 and a phase from t1 until t2 where maximum power is provided if demanded by the FB signal.
Figure 4
Soft Start
At the beginning of the Startup Phase, the IC provides a Soft Start duration whereby it controls the maximum primary current by means of a duty cycle limitation. A signal VSoftS which is generated by the external capacitor CSofts in combination with the internal pull up resistor RSoftS, determines the duty cycle until VSoftS exceeds 4V. When the Soft Start begins, CSoftS is immediately charged up to approx. 1V by T2. Therefore the Soft Start Phase takes
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F3 ICE3BS02L
Functional Description 3.4 PWM Section
0.72 Oscillator Duty Cycle max Clock
VCC
PWM Section
PWM-Latch 1
Z1
Gate
Soft Start Comparator PWM Comparator Current Limiting
FF1 1 G8 S R Q
Gate Driver & G9
Figure 7
Gate Driver
The driver-stage is optimized to minimize EMI and to provide high circuit efficiency. This is done by reducing the switch on slope when exceeding the external Power Switch threshold. This is achieved by a slope control of the rising edge at the driver's output (see Figure 8).
Gate
Figure 6 PWM Section
VGate
ca. t = 130ns
3.4.1 Oscillator The oscillator generates a fixed frequency. The switching frequency for ICE3BS02L is fOSC = 67kHz. A resistor, a capacitor and a current source and current sink which determine the frequency are integrated. The charging and discharging current of the implemented oscillator capacitor are internally trimmed, in order to achieve a very accurate switching frequency. The ratio of controlled charge to discharge current is adjusted to reach a maximum duty cycle limitation of Dmax=0.72. 3.4.2 PWM-Latch FF1 The oscillator clock output provides a set pulse to the PWMLatch when initiating the external Power Switch conduction. After setting the PWM-Latch can be reset by the PWM comparator, the Soft Start comparator or the Current-Limit comparator. In case of resetting, the driver is shut down immediately. 3.4.3 Gate Driver The Gate Driver is a fast totem pole gate drive which is designed to avoid cross conduction currents and which is equipped with a zener diode Z1 (see Figure 7) in order to improve the control of the Gate attached power transistors as well as to protect them against undesirable gate overvoltages.
CLoad = 1nF 5V
t
Figure 8 Gate Rising Slope Thus the leading switch on spike is minimized. When the external Power Switch is switched off, the falling shape of the driver is slowed down when reaching 2V to prevent an overshoot below ground. Furthermore the driver circuit is designed to eliminate cross conduction of the output stage. During powerup when VCC is below the undervoltage lockout threshold VVCCoff, the output of the Gate Driver is low to disable power transfer to the secondary side.
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F3 ICE3BS02L
Functional Description 3.5
PWM Latch FF1
Current Limiting
Latched Off Mode Current Limiting Spike Blanking 190ns Propagation-Delay Compensation Vcsth C10 PWM-OP & G10 C12 0.257V 1.66V C11
Latched Mode by the comparator C11 a spike blanking with 190ns is integrated in the output path of comparator C11. 3.5.1 Leading Edge Blanking
VSense
Vcsth tLEB = 220ns
Leading Edge Blanking 220ns
t
Figure 10 Leading Edge Blanking Each time when the external Power Switch is switched on, a leading edge spike is generated due to the primary-side capacitances and secondary-side rectifier reverse recovery time. This spike can cause the gate drive to switch off unintentionally. To avoid a premature termination of the switching pulse, this spike is blanked out with a time constant of tLEB = 220ns. During this time, the gate drive will not be switched off.
Active Burst Mode
10k D1
1pF
CS
Figure 9 Current Limiting Block
3.5.2
Propagation Delay Compensation
There is a cycle by cycle Current Limiting realized by the Current-Limit comparator C10 to provide an overcurrent detection. The source current of the external Power Switch is sensed via an external sense resistor RSense . By means of RSense the source current is transformed to a sense voltage VSense which is fed into the pin CS. If the voltage VSense exceeds the internal threshold voltage Vcsth the comparator C10 immediately turns off the gate drive by resetting the PWM Latch FF1. A Propagation Delay Compensation is added to support the immediate shut down without delay of the Power Switch in case of Current Limiting. The influence of the AC input voltage on the maximum output power can thereby be avoided. To prevent the Current Limiting from distortions caused by leading edge spikes a Leading Edge Blanking is integrated in the current sense path for the comparators C10, C12 and the PWM-OP. The output of comparator C12 is activated by the Gate G10 if Active Burst Mode is entered. Once activated the current limiting is thereby reduced to 0.257V. This voltage level determines the power level when the Active Burst Mode is left if there is a higher power demand. A further comparator C11 is implemented to detect dangerous current levels which could occur if there is a short winding in the transformer or the secondary diode is shorten. To ensure that there is no accidentally entering of the
In case of overcurrent detection, the switch-off of the external Power Switch is delayed due to the propagation delay of the circuit. This delay causes an overshoot of the peak current Ipeak which depends on the ratio of dI/dt of the peak current (see Figure 11).
Signal2 ISense Ipeak2 Ipeak1 ILimit IOvershoot2
Signal1 tPropagation Delay
IOvershoot1
t
Figure 11 Current Limiting The overshoot of Signal2 is bigger than of Signal1 due to the steeper rising waveform. This change in the slope is depending on the AC input voltage. Propagation Delay Compensation is integrated to limit the overshoot dependency on dI/dt of the rising primary current. That means the propagation delay time between exceeding the current sense threshold Vcsth and the switch off of the external Power Switch is compensated over temperature
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Functional Description
within a wide range. Current Limiting is now possible in a very accurate way. E.g. Ipeak = 0.5A with RSense = 2. Without Propagation Delay Compensation the current sense threshold is set to a static voltage level Vcsth=1V. A current ramp of dI/dt = 0.4A/s, that means dVSense/dt = 0.8V/s, and a propagation delay time of i.e. tPropagation Delay =180ns leads then to an Ipeak overshoot of 14.4%. By means of propagation delay compensation the overshoot is only about 2% (see Figure 12).
with compensation without compensation
with an Adjustable Blanking Window which is depending on the external Soft Start capacitor. By means of this Adjustable Blanking Window, the IC avoids entering into these two modes accidentally. Furthermore it also provides a certain time whereby the overload detection is delayed. This delay is useful for applications which normally works with a low current and occasionally require a short duration of high current. 3.6.1 Adjustable Blanking Window
V
1,3 1,25 1,2
SoftS
6.5V 5k RSoftS
VSense
1,15 1,1 1,05 1 0,95 0,9 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2
4.4V 1 S1 G2
V s
dVSense dt
Figure 12
Overcurrent Shutdown
5.4V 4.8V
C3
The Propagation Delay Compensation is realized by means of a dynamic threshold voltage Vcsth (see Figure 13). In case of a steeper slope the switch off of the driver is earlier to compensate the delay.
& C4 G5
VOSC
Auto Restart Mode
max. Duty Cycle
Active Burst Mode
off time
VSense Vcsth
Propagation Delay
t
FB
C5 1.32V
& G6
Control Unit
Figure 14
Adjustable Blanking Window
Signal1
Figure 13
Signal2
t
Dynamic Voltage Threshold Vcsth
3.6
Control Unit
The Control Unit contains the functions for Active Burst Mode, Auto Restart Mode and Latched Off Mode. The Active Burst Mode and the Auto Restart Mode are combined
VSoftS is clamped at 4.4V by the closed switch S1 after the SMPS is settled. If overload occurs VFB is exceeding 4.8V. Auto Restart Mode can't be entered as the gate G5 is still blocked by the comparator C3. But after VFB has exceeded 4.8V the switch S1 is opened via the gate G2. The external Soft Start capacitor can now be charged further by the integrated pull up resistor RSoftS. The comparator C3 releases the gates G5 and G6 once VSofts has exceeded 5.4V. Therefore there is no entering of Auto Restart Mode possible during this charging time of the external capacitor CSoftS. The
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F3 ICE3BS02L
Functional Description
same procedure happens to the external Soft Start capacitor if a low load condition is detected by comparator C5 when VFB is falling below 1.32V. Only after VSoftS has exceeded 5.4V and VFB is still below 1.32V Active Burst Mode is entered. 3.6.2 Active Burst Mode The controller provides Active Burst Mode for low load conditions at VOUT. Active Burst Mode increases significantly the efficiency at light load conditions while supporting a low ripple on VOUT and fast response on load jumps. During Active Burst Mode which is controlled only by the FB signal the IC is always active and can therefore immediately response on fast changes at the FB signal. The Startup Cell is kept switched off to avoid increased power losses for the self supply. releases the gate G6 to enter the Active Burst Mode. The time window that is generated by combining the FB and SoftS signals with gate G6 avoids a sudden entering of the Active Burst Mode due to large load jumps. This time window can be adjusted by the external capacitor CSoftS. After entering Active Burst Mode a burst flag is set and the internal bias is switched off in order to reduce the current consumption of the IC down to approx. 1.05mA. In this Off State Phase the IC is no longer self supplied so that therefore CVCC has to provide the VCC current (see Figure 16). Furthermore gate G11 is then released to start the next burst cycle once VFB has 3.4V exceeded. It has to be ensured by the application that the VCC remains above the Undervoltage Lockout Level of 8.5V to avoid that the Startup Cell is accidentally switched on. Otherwise power losses are significantly increased. The minimum VCC level during Active Burst Mode is depending on the load conditions and the application. The lowest VCC level is reached at no load conditions at VOUT. 3.6.2.2 Working in Active Burst Mode After entering the Active Burst Mode the FB voltage rises as VOUT starts to decrease due to the inactive PWM section. Comparator C6a observes the FB signal if the voltage level 4V is exceeded. In that case the internal circuit is again activated by the internal Bias to start with switching. As now in Active Burst Mode the gate G10 is released the current limit is only 0.257V to reduce the conduction losses and to avoid audible noise. If the load at VOUT is still below the starting level for the Active Burst Mode the FB signal decreases down to 3.4V. At this level C6b deactivates again the internal circuit by switching off the internal Bias. The gate G11 is released as after entering Active Burst Mode the burst flag is set. If working in Active Burst Mode the FB voltage is changing like a saw tooth between 3.4V and 4V (see Figure 16). 3.6.2.3 Leaving Active Burst Mode The FB voltage immediately increases if there is a high load jump. This is observed by comparator C4. As the current limit is ca. 26% during Active Burst Mode a certain load jump is needed that FB can exceed 4.8V. At this time C4 resets the Active Burst Mode which also blocks C12 by the
SoftS
6.5V 5k? 4.4V RSoftS Internal Bias
S1
Current Limiting & C3
5.4V 4.8V C4
G10
FB
1.32V
C5
& G6
Active Burst Mode
C6a 4.0V
C6b 3.4V Control Unit
& G11
Figure 15
Active Burst Mode
The Active Burst Mode is located in the Control Unit. Figure 15 shows the related components. 3.6.2.1 Entering Active Burst Mode The FB signal is always observed by the comparator C5 if the voltage level falls below 1.32V. In that case the switch S1 is released which allows the capacitor CSoftS to be charged starting from the clamped voltage level at 4.4V in normal operating mode. If VSoftS exceeds 5.4V the comparator C3
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F3 ICE3BS02L
Functional Description
gate G10. Maximum current can now be provided to stabilize VOUT. 3.6.3 Protection Modes The IC provides several protection features which are separated into two categories. Some enter Latched Off Mode, the others enter Auto Restart Mode. The Latched Off Mode can only be reset if VCC is falling below 6V. Both modes prevent the SMPS from destructive states. The following table shows the relationship between possible system failures and the chosen protection modes. VCC Overvoltage
t Blanking W indow 5.40V 4.40V
VFB
4.80V 4.00V 3.40V 1.32V
Entering Active Burst Mode
Leaving Active Burst Mode
Latched Off Mode Latched Off Mode Latched Off Mode Auto Restart Mode Auto Restart Mode Auto Restart Mode Auto Restart Mode
VSoftS
Overtemperature Short Winding/Short Diode Overload Open Loop VCC Undervoltage Short Optocoupler
VCS
1.00V 0.257V Current limit level during Active Burst Mode
t
3.6.3.1
Latched Off Mode
CS
Latched Off Mode Reset VVCC < 6V
VVCC
t
C11 1.66V
Spike Blanking 190ns
1 G3
Latched Off Mode
8.5V
VCC
IVCC
7.2mA
t
C1 21V
& G1
Spike Blanking 8.0us
4.8V C4
1.05mA
Thermal Shutdown
Voltage Reference
VOUT
Max. Ripple < 1%
t
Tj >140C Control Unit
FB
Figure 17
t
Latched Off Mode
Figure 16
Signals in Active Burst Mode
The VCC voltage is observed by comparator C1 if 21V is exceeded. The output of C1 is combined with the output of C4 which observes FB signal if 4.8V is exceeded. Therefore the overvoltage detection is only activated if the FB signal is
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Functional Description
outside the operating range > 4.8V, e.g. when Open Loop happens. This means any small voltage overshoots of VVCC during normal operating can not start the Latched Off Mode. The internal Voltage Reference is switched off once Latched Off Mode is entered in order to reduce the current consumption of the IC as much as possible. Latched Off Mode can only be reset by decreasing VVCC < 6V. In this stage, only the UVLO is working which controls the Startup Cell by switching on/off at VVCCon/VVCCoff. During this phase, the average current consumption is only 300A. As there is no longer a self- supply by the auxiliary winding, VCC drops. The Undervoltage Lockout switches on the integrated Startup Cell when VCC falls below 8.5V. The Startup Cell is switched off again when VCC has exceeded 15V. Once the Latched Off Mode was entered, there is no Start Up Phase after VCC has exceeded the switch-on level of the Undervoltage Lockout. Therefore VCC changes between the switch-on and switch-off levels of the Undervoltage Lockout with a saw tooth shape (see Figure 18). 3.6.3.2 Auto Restart Mode
SoftS
6.5V 5k RSoftS
4.4V 1 S1 G2 Voltage Reference C3 5.4V 4.8V C4 & G5 Auto Restart Mode Control Unit
VVCC
15V
FB
Figure 19 Auto Restart Mode
8.5V
IVCCStart
1.05mA
t
VOUT
Figure 18 Signals in Latched Off Mode
t
The Thermal Shutdown block monitors the junction temperature of the IC. After detecting a junction temperature higher than 140C, Latched Off Mode is entered. The signals coming from the temperature detection and VCC overvoltage detection are fed into a spike blanking with a time constant of 8.0s to ensure system reliability. Furthermore, a short winding or short diode on the secondary side can be detected by the comparator C11 which is in parallel to the propagation delay compensated current limit comparator C10. In normal operating mode comparator C10 keeps the maximum level of the CS signal at 1V. If there is a failure such as short winding or short diode, C10 is no longer able to limit the CS signal at 1V. C11 detects then the over current and enters immediately the Latched Off Mode to keep the SMPS in a safe stage.
In case of Overload or Open Loop, FB exceeds 4.8V which will be observed by C4. At this time S1 is released that VSoftS can increase. If VSoftS exceeds 5.4V which is observed by C3, Auto Restart Mode is entered as both inputs of the gate G5 are high. In combining the FB and SoftS signals, there is a blanking window generated which prevents the system to enter Auto Restart Mode due to large load jumps. This time window is the same as for the Active Burst Mode and can therefore be adjusted by the external CSoftS. In case of VCC undervoltage, the IC enters into the Auto Restart Mode and starts a new startup cycle. Short Optocoupler also leads to VCC undervoltage as there is no self supply after activating the internal reference and bias. In contrast to the Latched Off Mode, there is always a Startup Phase with switching cycles in Auto Restart Mode. After this Start Up Phase, the conditions are again checked whether the failure mode is still present. Normal operation is resumed once the failure mode is removed that had caused the Auto Restart Mode.
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Electrical Characteristics
4
Note:
Electrical Characteristics
All voltages are measured with respect to ground (Pin 8). The voltage levels are valid if other ratings are not violated.
4.1
Note:
Absolute Maximum Ratings
Absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction of the integrated circuit. For the same reason make sure, that any capacitor that will be connected to pin 7 (VCC) is discharged before assembling the application circuit. Symbol VHV VVCC VFB VSoftS VGate VCS Tj TS Ptot RthJA VESD -0.3 -0.3 -0.3 -0.3 -0.3 -40 -55 Limit Values min. max. 500V 22 6.5 6.5 22 6.5 150 150 0.9 90 3 V V V V V V C C W K/W kV Human body model1) Tamb < 50C Internally clamped at 11.5V Unit Remarks
Parameter HV Voltage VCC Supply Voltage FB Voltage SoftS Voltage Gate Voltage CS Voltage Junction Temperature Storage Temperature Total Power Dissipation Thermal Resistance Junction-Ambient ESD Capability(incl. HV Pin)
1)
According to EIA/JESD22-A114-B (discharging a 100pF capacitor through a 1.5k series resistor)
4.2
Note:
Operating Range
Within the operating range the IC operates as described in the functional description. Symbol VVCC Limit Values min. max. 20 130 V C Max value limited due to thermal shut down of controller VVCCoff -25 Unit Remarks
Parameter VCC Supply Voltage
Junction Temperature of Controller TjCon
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F3 ICE3BS02L
Electrical Characteristics 4.3
4.3.1 Note:
Characteristics
Supply Section The electrical characteristics involve the spread of values within the specified supply voltage and junction temperature range TJ from - 25 C to 130 C. Typical values represent the median values, which are related to 25C. If not otherwise stated, a supply voltage of VCC = 15 V is assumed. Symbol min. IVCCstart IVCCcharge1 IVCCcharge2 IStartLeak IVCCsup1 0.55 Limit Values typ. 160 1.05 0.88 0.2 5.5 6.5 300 300 max. 220 1.60 20 7.0 8.0 A mA mA A mA mA A A VSoftS = 4.4V IFB = 0, CLoad=1nF IFB = 0 ISofts = 0 IFB = 0 ISofts = 0 VVCC =15V VFB = 3.7V, VSoftS = 4.4V VVCC = 9.5V VFB = 3.7V, VSoftS = 4.4V VVCC =14V VVCC = 0V VVCC =14V VVCC =16V, VHV = 450V Unit Test Condition
Parameter Start Up Current VCC Charge Current Leakage Current of Start Up Cell Supply Current with Inactive Gate
Supply Current with Active Gate IVCCsup2 Supply Current in Latched Off Mode Supply Current in Auto Restart Mode with Inactive Gate Supply Current in Active Burst Mode with Inactive Gate VCC Turn-On Threshold VCC Turn-Off Threshold VCC Turn-On/Off Hysteresis IVCClatch IVCCrestart
IVCCburst1 IVCCburst2 VVCCon VVCCoff VVCChys
14.2 8.0 -
1.05 0.95 15.0 8.5 6.5
1.25 1.15 15.8 9.0 -
mA mA V V V
4.3.2 Parameter
Internal Voltage Reference Symbol min. VREF 6.37 Limit Values typ. 6.50 max. 6.63 V measured at pin FB IFB = 0 Unit Test Condition
Trimmed Reference Voltage
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Electrical Characteristics
4.3.3 Parameter Fixed Oscillator Frequency Max. Duty Cycle Min. Duty Cycle PWM-OP Gain Voltage Ramp Max Level VFB Operating Range Min Level VFB Operating Range Max level FB Pull-Up Resistor SoftS Pull-Up Resistor
1)
PWM Section Symbol min. fOSC1 fOSC2 Dmax Dmin AV VMax-Ramp VFBmin VFBmax RFB RSoftS 61 63 0.67 0 3.5 0.3 16 39 Limit Values typ. 67 67 0.72 3.7 0.85 0.7 20 50 max. 73 71 0.77 3.9 4.75 27 62 V V V k k CS=1V, limited by Comparator C41) VFB < 0.3V kHz kHz Tj = 25C Unit Test Condition
The parameter is not subjected to production test - verified by design/characterization Control Unit Symbol min. VSoftSC2 VSoftSclmp VSoftSC3 ISoftSstart VFBC4 VFBC5 VFBC6a VFBC6b 3.85 4.23 5.20 4.62 1.23 3.85 3.25 Limit Values typ. 4.00 4.40 5.40 1.3 4.80 1.30 4.00 3.40 max. 4.15 4.57 5.60 4.98 1.37 4.15 3.55 V V V mA V V V V VFB > 5V VFB = 4V VFB > 5V VSoftS = 0V VSoftS > 5.6V VSoftS > 5.6V After Active Burst Mode is entered After Active Burst Mode is entered Unit Test Condition
4.3.4 Parameter
Deactivation Level for SoftS Comparator C7 by C2 Clamped VSoftS Voltage during Normal Operating Mode Activation Limit of Comparator C3 SoftS Startup Current Over Load & Open Loop Detection Limit for Comparator C4 Active Burst Mode Level for Comparator C5 Active Burst Mode Level for Comparator C6a Active Burst Mode Level for Comparator C6b
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Electrical Characteristics
Parameter Overvoltage Detection Limit Latched Thermal Shutdown1) Spike Blanking Power Down Reset for Latched Mode
1)
Symbol min. VVCCOVP TjSD tSpike VVCCPD 20 130 4.0
Limit Values typ. 21 140 8.0 6.0 max. 22 150 7.5
Unit V C s V
Test Condition VFB > 5V
After Latched Off Mode is entered
The parameter is not subjected to production test - verified by design/characterization The trend of all the voltage levels in the Control Unit is the same regarding the deviation except VVCCOVP and VVCCPD Current Limiting Symbol min. Vcsth 0.97 Limit Values typ. 1.02 max. 1.07 V dVsense / dt = 0.6V/s (see Figure 12) Unit Test Condition
Note: 4.3.5
Parameter Peak Current Limitation (incl. Propagation Delay Time of external MOS) Peak Current Limitation during Active Burst Mode Leading Edge Blanking CS Input Bias Current Over Current Detection for Latched Off Mode CS Spike Blanking for Comparator C11
VCS2 tLEB ICSbias VCS1 tCSspike
0.232 -1.0 1.570 -
0.257 220 -0.2 1.66 190
0.282 0 1.764 -
V ns A V ns VSoftS = 4.4V VCS =0V
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Electrical Characteristics
4.3.6 Parameter GATE Low Voltage Driver Section Symbol min. VGATElow -0.2 GATE High Voltage VGATEhigh GATE Rise Time (incl. Gate Rising Slope) GATE Fall Time GATE Current, Peak, Rising Edge GATE Current, Peak, Falling Edge
1) 2)
Limit Values typ. 0.8 1.6 0.2 11.5 10.5 7.5 150 55 max. 1.2 1.5 2.0 0.7
Unit V V V V V V V V ns ns A A
Test Condition VVCC = 5 V IGate = 5 mA VVCC = 5 V IGate = 20 mA IGate = 0 A IGate = 20 mA IGate = -20 mA VVCC = 20V CL = 4.7nF VVCC = 11V CL = 4.7nF VVCC = VVCCoff + 0.2V CL = 4.7nF VGate = 2V ...9V1) CL = 4.7nF VGate = 9V ...2V1) CL = 4.7nF CL = 4.7nF2) CL = 4.7nF2)
trise tfall IGATE IGATE
-0.5 -
Transient reference value The parameter is not subjected to production test - verified by design/characterization
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F3 ICE3BS02L
Outline Dimension
5
Outline Dimension
PG-DIP-8-6 (Leadfree Plating Plastic Dual In-Line Outline)
Figure 20 PG-DIP-8-6 (Leadfree Plating Plastic Dual In-Line Outline)
Dimensions in mm
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